1. Field of the Invention
The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method for manufacturing a metal-insulator-metal (MIM) capacitor of a semiconductor memory device, which has lower and upper electrodes formed of metal, controlling a thermal budget.
2. Description of the Related Art
As the area of the cross section of cells decreases due to increases in the integration density of semiconductor devices, it becomes more difficult to obtain sufficient capacitance to operate a device. Accordingly, in order to reduce the thickness of dielectric layers in the manufacture of a capacitor necessary to operate a semiconductor memory device of Gigabit capacity or more and increase the effective area of the cross section of the capacitor, various studies have been carried out to form a storage node having a three-dimensional structure. However, it is very difficult to obtain effective capacitance required to operate a semiconductor memory device of Gigabit or higher capacity through the use of a conventional oxide-nitride-oxide (ONO) dielectric layer. Accordingly, a high dielectric layer which is formed of metal oxide, such as Ta2O5 or TaON, and a material having a perovskite structure, such as (Ba, Sr)TiO3 (BST), SrTiO3 (STO), BaTiO3, Pb(Zr, Ti)O3 (PZT), or (Pb, La)(Zr, Ti)O3(PLZT), has been suggested.
In the manufacture of a capacitor using such a high dielectric layer, it is more preferable to manufacture a MIM capacitor than to manufacture a capacitor employing a polysilicon electrode because the polysilicon electrode needs a low dielectric layer for preventing a dielectric layer from reacting with the polysilicon electrode, and thus there is a limit to which the capacitance can be increased using the polysilicon electrode. On the other hand, in the case of the MIM capacitor using an electrode formed of a metal having a high work function, a barrier layer is formed at the interface between the metal electrode and a dielectric layer and controls leakage current. Accordingly, it is possible to obtain a capacitor having stable electrical characteristics without introducing a low dielectric layer and thus increase capacitance by reducing the thickness of a dielectric layer.
In order to obtain a capacitor having high dielectric characteristics required to operate a semiconductor memory device of Gigabit or higher capacity from a MIM capacitor, a crystallized dielectric layer must be used because a dielectric material, such as Ta2O4, TaON, BST, or STO, which is generally used to form a dielectric layer of a MIM capacitor, has 2-10 times better dielectric characteristics in a crystallized state than in an amorphous state.
There are methods for crystallizing a dielectric layer including a method for forming a crystalline dielectric layer by depositing and growing a dielectric layer at a high temperature and a method for forming a crystalline dielectric layer by depositing an amorphous dielectric layer and heat-treating the amorphous dielectric layer. However, the method for crystallizing a dielectric layer by depositing the dielectric layer at a high temperature has problems in which a high temperature necessary to sufficiently crystallize the dielectric layer may cause the step coverage characteristics of the dielectric layer to deteriorate and may oxidize a lower electrode and a TiN-based diffusion barrier layer. Accordingly, the method for crystallizing a dielectric layer by depositing an amorphous dielectric layer and heat-treating the amorphous dielectric layer at a high temperature is considered to be more effective to manufacture a MIM capacitor having a crystalline dielectric layer.
According to a conventional method for manufacturing a capacitor, in order to manufacture a MIM capacitor using a method for forming a crystalline dielectric layer through a heat treatment, a lower electrode is formed on a semiconductor substrate, on which underlying structures are already formed. Next, an amorphous dielectric layer is formed on the lower electrode and is heat-treated at a high temperature to be crystallized. Next, an upper electrode is formed on the crystallized dielectric layer. Here, in order to sufficiently crystallize the amorphous dielectric layer, a heat treatment performed at a high temperature is necessary. However, according to this conventional method, the electrodes may cause tensile stress affecting the dielectric layer due to the difference in thermal expansion coefficients between the electrodes and the dielectric layer and a coarsening effect caused by the grain growth of the material of the electrodes as well as the crystallization of the amorphous dielectric layer when heat-treating the amorphous dielectric layer. Accordingly, the physical and electrical characteristics of the MIM capacitor may deteriorate.
In order to solve the above problems, according to another conventional method for manufacturing a MIM capacitor, a lower electrode is heat treated before deposition of a dielectric layer. This method prevents tensile stress from affecting the dielectric layer and prevents the lower electrode from being deformed during the heat treatment of the dielectric layer by allowing the coarsening effect caused by the grain growth of the material of the lower electrode to be produced before depositing the dielectric layer. However, this method has a problem in that discontinuities may be generated at the lower electrode because of coagulation of the lower electrode when heat treating the lower electrode. In addition, even if the lower electrode is heat treated, it is impossible to obtain a stable leakage current value necessary to operate a device. Accordingly, it is difficult to obtain a MIM capacitor having stable electrical characteristics through heat treatment of the lower electrode.
To solve the above-described problems, it is an object of the present invention to provide a method for manufacturing a MIM capacitor of a semiconductor memory device which is capable of preventing a lower electrode from being deformed during heat treating a dielectric layer to be crystallized and thus improving the physical and electrical characteristics of the MIM capacitor.
In accordance with the inveniton, there is provided a method for manufacturing a capacitor of a semiconductor memory device. A lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.
The lower electrode may be formed of a noble metal, conductive noble metal oxide, or conductive metal oxide. Preferably, the lower electrode is formed of Pt, Ru, Ir, PtO, RuO2, IrO2, SrRuO3, BaSrRuO3, or LaScCo.
The dielectric layer may be formed of a metal oxide layer or a material layer having a perovskite structure. Preferably, the dielectric layer is a mono layer including a material selected from among Ta2O5, Al2O3, TaON, (Ba, Sr)TiO3(BST), SrTiO3(STO), BaTiO3(BTO), PbTiO3, Pb(Zr, Ti)O3(PZT), SrBi2Ta2O9(SBT), (Pb, La)(Zr, Ti)O3, and Bi4Ti3O12 or a composite layer of any of the above.
In one embodiment, in heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets are adjusted by controlling any of the temperature, time, and method of their respective heat treatments.
In one embodiment, in heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets are adjusted by controlling the temperature of their respective heat treatments. For example, the dielectric layer can be heat-treated at a first temperature which is higher than the crystallization temperature of the dielectric layer, and the lower electrode can be heat-treated at a second temperature which is higher than the first temperature by 50-200xc2x0 C. In heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets can be adjusted by controlling the time of their respective heat treatments. For example, the period of time for which the lower electrode is heat-treated can be longer than the period of time for which the dielectric layer is heat-treated. In a case where the lower electrode and the dielectric layer are heat-treated using furnaces, the period of time for which the lower electrode is heat-treated can be longer than the period of time for which the dielectric layer is heat-treated by 30 minutes-2 hours. In heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets can be adjusted by using different heat-treatment methods. For example, a heat treatment using a furnace can be used to obtain the first thermal budget in heat-treating the lower electrode, and rapid thermal annealing (RTA) or plasma annealing can be used to obtain the second thermal budget in crystallizing the dielectric layer. Alternatively, in heat-treating the lower electrode and crystallizing the dielectric layer, the first and second thermal budgets may also be adjusted by controlling at least two out of the temperature, time, and method of their respective heat treatments.
The lower electrode may be heat-treated at a temperature of 500-850xc2x0 C. In addition, the lower electrode may be heat-treated in a gas atmosphere generated from a gas selected from among N2, O2, H2, N2O, NO, NO2, Ar, and O3. Alternatively, the lower electrode may be heat-treated in a vacuum atmosphere.
The dielectric layer may be heat-treated in a gas atmosphere generated from a gas selected from among N2, O2, H2, N2O, NO, NO2, Ar, and O3. The dielectric layer may be heat-treated in a vacuum or plasma atmosphere.
The method for manufacturing a capacitor of a semiconductor memory device according to the first embodiment of the present invention may further include forming a coagulation prevention layer on the lower electrode. Here, the lower electrode is heat-treated with the first thermal budget after forming the coagulation prevention layer. The coagulation prevention layer may be a mono layer including a material selected from among SiO2, photoresist, Si3N4, Ta2O5, Al2O3, SrTiO3(STO), (Ba, Sr)TiO3(BST), PbTiO3, Pb(Zr, Ti)O3(PZT), SrBi2Ta2O5(SBT), (Pb, La)(Zr, Ti)O3, Bi4Ti3O12, BaTiO3(BTO), and organic polymer or a composite layer of the above. The method for manufacturing a capacitor of a semiconductor memory device according to the first embodiment of the present invention may further include removing the coagulation prevention layer after heat-treating the lower electrode with the first thermal budget. The coagulation prevention layer may be removed by dry or wet etching.
The method for manufacturing a capacitor of a semiconductor memory device may further include forming a sacrificial insulating layer pattern on the semiconductor substrate to define a storage node hole. Here, the lower electrode is formed at the sidewalls of the sacrificial insulating layer pattern in the storage node hole. The sacrificial insulating layer pattern can be formed of SiO2.
In this embodiment, in order to form the lower electrode, a conductive layer is formed covering the top surface and sidewalls of the sacrificial insulating layer pattern and the bottom surface of the storage node hole. An etching stop layer is formed to a sufficient thickness to completely fill the storage node hole on the conductive layer. A concave-type lower electrode comprised of the conductive layer remaining only in the storage node hole is formed by removing portions of the etching stop layer and the conductive layer until the conductive layer covering the top surface of the sacrificial insulating layer pattern is removed. The etching stop layer remaining in the storage node hole is removed. The conductive layer may be formed of Pt, Ru, Ir, PtO, RuO2, IrO2, SrRuO3, BaSrRuO3, or LaScCo. Here, the lower electrode is heat-treated with the first thermal budget using the etching stop layer as a coagulation prevention layer before removing the etching stop layer remaining in the storage node hole.
The sacrificial insulating layer pattern may have a structure in which a first insulating layer pattern, an etching stopper pattern, and a second insulating layer pattern are sequentially stacked. In order to form the lower electrode, a conductive layer is formed covering the top surface and sidewalls of the sacrificial insulating layer pattern and the bottom surface of the storage node hole. An etching stop layer is formed to a sufficient thickness to completely fill the storage node hole on the conductive layer. A cylinder-type lower electrode comprised of the conductive layer remaining only in the storage node hole is formed by removing portions of the etching stop layer and the conductive layer until the conductive layer covering the sacrificial insulating layer pattern is removed. The etching stop layer remaining in the storage node hole is removed. Here, the lower electrode is heat-treated with the first thermal budget using the etching stop layer as a coagulation prevention layer before removing the etching stop layer remaining in the storage node hole. The method for manufacturing a capacitor of a semiconductor memory device according to the first embodiment of the present invention may further include removing the first insulating layer pattern after heat-treating the lower electrode with the first thermal budget. Here, the dielectric layer is formed on the etching stopper pattern and the lower electrode.
In order to form the lower electrode, a conductive layer is formed to a sufficient thickness to completely fill the storage node hole on the semiconductor substrate on which the sacrificial insulating layer pattern is formed. A stack-type lower electrode comprised of the conductive layer remaining only in the storage node hole is formed by removing the conductive layer on the sacrificial insulating layer pattern.
The method for manufacturing a capacitor of a semiconductor memory device according to the first embodiment of the present invention may further include forming an upper electrode on the dielectric layer. Here, the dielectric layer may be heat-treated with the second thermal budget before or after forming the upper electrode. The upper electrode may be formed of a noble metal, conductive noble metal oxide, or conductive metal oxide. Preferably, the upper electrode is formed of Pt, Ru, Ir, PtO, RuO2, IrO2, SrRuO3, BaSrRuO3, or LaScCo.
In accordance with the invention, there is provided another method for manufacturing a capacitor of a semiconductor memory device. A conductive layer is formed on a semiconductor substrate. The conductive layer is heat-treated with a first thermal budget. A lower electrode is formed by patterning the conductive layer. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget. An upper electrode is formed on the dielectric layer.
The method for manufacturing a capacitor of a semiconductor memory device according to the second embodiment of the present invention may further include forming an etching stop layer on the conductive layer and removing the etching stop layer after forming the lower electrode. Here, the conductive layer is heat-treated with the first thermal budget after forming the etching stop layer.
According to the present invention, a lower electrode is heat-treated with a thermal budget greater than a thermal budget applied to heat-treat a dielectric layer to be crystallized before the dielectric layer is deposited on the lower electrode. Accordingly, the lower electrode can be sufficiently coarsened through grain growth before the heat treatment of the dielectric layer. In addition, it is possible to obtain a capacitor having stable leakage current characteristics necessary to operate a device by preventing the lower electrode from being deformed during the heat treatment of the dielectric layer and thus effectively preventing tensile stress from affecting the dielectric layer.